The power FET has become a limiting component in many power management circuits used to regulate voltage and/or current in DC-DC converters, AC-DC inverters, or AC transformers. In recent decades, significant efforts have been made to boost the power FET's output currents and switching speeds to keep pace with the integrated circuit “transistor shrinks”. The smaller transistors increase system switching speeds and the transistor densities within an integrated circuit. Higher densities allow vastly more transistors to be incorporated into a single semiconductor chip, causing it to require larger operational currents. Similarly, smaller transistor dimensions also increase operational system speeds. Any inability to supply a combination of larger currents at higher switching speeds leaves many systems “under powered”. This is particularly the case in multi-core microprocessors where the inability to supply required current at suitably higher speed impairs reliable data transfer with external memory circuits. As a result of this deficiency, processor cores will typically operate at 25%-30% utilization rates. This problem becomes more acute when processor cores are configured in parallel. For instance, a 16 core microprocessor array will function slower than a 4 core microprocessor array due to in adequate power refresh cycling. Therefore, it is desirable to increase power efficiencies by developing power FETs that enable arbitrarily high currents to be switched at arbitrarily high switching speeds. While higher switching speed and current levels are of specific benefit to power FETs, methods that enable switching speeds above 400 MHz or over a distinct band of frequencies could be usefully applied to many other FET applications. Therefore, generalized methods to tune a FET's switching speed and/or current output is also desirable.
Co-location of high efficiency switched-mode power management devices with one or more processor cells also reduces the overall system power losses through much shorter interconnect circuitry. Methods and apparatus that improve the efficiency of supplied power to a processor core by co-locating power management in immediate proximity to computational die are therefore enabling and desirable to the enhanced utilization of microprocessor arrays and the improved operational efficiency of high-speed computational systems.
Most approaches to increase power FET switching speeds have focused on reducing the transistor gate capacitance. This is done generally by making the gate electrode smaller, and by using more sophisticated electronic doping configurations within the transistor junction. A significant drawback to these elements of the prior art is the generation of larger quantities of heat, which is undesirable and must be properly managed to safeguard the performance of neighboring semiconductor devices. While smaller gate structures lower capacitance, they also increase current densities flowing through the transistor junction to attain high currents, which, in-turn, increases generated heat to levels that prevent co-location of power management in close proximity to computational semiconductor die. Higher current levels often require thermal management mechanisms to be added to the system to drain the excess heat generated by the higher levels of resistive loss. Additional or more sophisticated thermal management requirements increase the cost and design complexity of the overall system. Prior art solutions advance improved doping topologies to reduce the ON-resistance of the power FET's transistor junction. However, the proposed solutions alone do not reduce ON-resistance to sufficiently low levels that allow power management systems to be monolithically integrated with or placed in close proximity to the active system devices, or to mitigate or eliminate thermal management devices from the power management system. This is a particular problem in power management systems that are assembled from discrete components. Therefore, it is also desirable to reduce the ON-resistance of a power FET by orders of magnitude to levels that mitigate or eliminate thermal management systems in a power management device.
Many power management systems are utilized in mobile platforms that are subject to frequent or unpredictable mechanical shock. Solder joints are used to electrically interconnect surface mounted passive components (resistors, capacitors, inductors) on a printed circuit board in electrical communication with one or more semiconductor die. Lead-free solders used to achieve modern environmental standards do not have the mechanical integrity of the lead-based solders they are replacing. Fractures in solder joints are the dominant cause for field failures in mobile systems. Additionally, solder joint failures in power management devices are the leading cause for grounding aircraft due to unscheduled maintenance. Therefore, methods that eliminate solder joints from a power management system by monolithically integrating all components on to a semiconductor die are also beneficial and a desirable objective of the present invention.
1. Description of the Prior Art
Yoshimochi, U.S. Pat. No. 7,459,749 B2, entitled HIGH SPEED POWER MOSFET, applies a low resistance layer to a gate structure buried within a channel to increase the power FET's switching speed.
Disney and Grabowski, U.S. Pat. No. 7,115,958 B2, entitled LATERAL POWER MOSFET FOR HIGH SWITCHING SPEEDS, instructs the use of field plates within a gate structure of a lateral field effect transistor to improve the propagation of gate signals within high voltage power transistors.
Saito and Omura, U.S. Pat. No. 6,967,374 B1, entitled POWER SEMICONDUCTOR DEVICE, instructs methods to reduce the ON resistance of a power switching element through the use of power MOSFETs electrically connected in parallel with Schottky barrier diodes to achieve a “soft-switching” operational mode, wherein they disclose various embodiments of MOSFET superjunction doping configurations.
Parker and Tanghe, U.S. Pat. No. 6,630,715 B2, entitled ASYMMETRICAL MOSFET LAYOUT FOR HIGH-CURRENT AND HIGH SPEED OPERATION, uses multiple metallization layers that overlay a source electrode on top of a drain and gate electrodes to modulate a surface FET at higher currents and speeds, and in particular disclose metallization layouts that minimize capacitive coupling and maximize current flows that mitigate failure modes due to electromigration.
Parks, U.S. Pat. No. 6,477,065 B2, entitled RESONANT GATE DRIVER, discloses the use of a resonant circuit to drive the gate of one or more vertical field effect transistors.
Calafut, U.S. Pat. No. 6,396,102 B1, entitled FIELD COUPLED POWER MOSFET BUS ARCHITECTURE USING TRENCH TECHNOLOGY, discloses the application of multiple gate trenches within the gate signal buses of a power MOSFET to suppress hot-carrier generation improve the voltage handling ability of the gate signal bus.
Hshieh and So, U.S. Pat. No. 6,025,230, entitled HIGH SPEED MOSFET POWER DEVICE WITH ENHANCED RUGGEDNESS FABRICATED BY SIMPLIFIED PROCESSES, disclose manufacturing methods and electronic doping patterns that enable a vertical power FET to operate at higher switching speed by reducing gate capacitance.
Sakamoto and Yoshida, U.S. Pat. No. 5,903,034, entitled SEMICONDUCTOR CIRCUIT DEVICE HAVING AN INSULATED-GATE TYPE TRANSISTOR, instruct the use of resistive, capacitive and reactive (transistor/diode) elements to reduce the parasitic capacitance within a control circuit that modulates a power FET when the two systems are embedded in the same semiconductor die.
Meyer et al., U.S. Pat. No. 5,665,618, entitled METHOD OF FORMING AN INTERBAND LATERAL RESONANT TUNNELING TRANSISTOR WITH SINGLE NARROW GATE ELECTRODE, discloses a quantum-effect device that utilizes resonant tunneling process in narrow-gap nano-structures to form a lateral transistor on a quantum wire.
Dansky et al., U.S. Pat. No. 5,287,016, entitled HIGH SPEED BIPOLAR FIELD EFFECT TRANSISTOR (BI-FET) CIRCUIT, uses multiple transistors and complementary clocks to achieve higher switching speeds with reduced power dissipation.
Ballga and Schlect, U.S. Pat. No. 4,967,243, entitled POWER TRANSISTOR STRUCTURE HIGH SPEED INTEGRAL ANTIPARALLEL SCHOTTKY DIODE, incorporates an integral Schottky diode in anti-parallel connection with the transistor to improve recovery characteristics and prevent forward voltage overshoot transients by conducting reverse currents through the device.
Nathanson et al., U.S. Pat. No. 3,590,343, entitled RESONANT GATE TRANSISTOR WITH FIXED POSITION ELECTRICALLY FLOATING GATE ELECTRODE IN ADDITION TO RESONANT MEMBER, utilizes a vibrating member, such as a cantilever, to control current modulation in a transistor gate by means of mechanical resonance.
Abele et al., U.S. patent application Ser. No. 12/850,126, entitled MICRORESONATOR, discloses the application of a micromechanical resonator within the gate of a transistor.
Weinstein and Bhave, U.S. patent application Ser. No. 12/811,552, entitled RESONANT BODY TRANSISTOR AND OSCILLATOR, disclose methods that couple a resonant body, or cavity that may or may not be filled with a dielectric material, with an inversion and/or an accumulation gate, to create transistor functionality.
Disney and Hsing, U.S. patent application Ser. No. 12/576,150, entitled POWER DEVICES WITH SUPERJUNCTIONS AND ASSOCIATED METHODS MANUFACTURING, disclose manufacturing methods to form vertical power FETs that contain “superjunctions” to reduce the device ON-resistance.
Gao et al., U.S. patent application Ser. No. 12/549,190, entitled SUPER JUNCTION TRENCH POWER MOSFET DEVICE FABRICATION, disclose methods to manufacture superjunction power FETs with reduced ON-resistance and improved breakdown voltages to improve device efficiency.
Masuda and Mori, U.S. patent application Ser. No. 12/127,782, entitled RESONANT CIRCUIT WITH FREQUENCY TUNABILITY, disclose integration of capacitors and inductors in a semiconductor chip to form resonant circuits that control signals that modulate one or more transconductance devices, such as an amplifier or a gyrator, co-located in the semiconductor chip.
2. Definition of Terms
The term “active component” is herein understood to refer to its conventional definition as an element of an electrical circuit that that does require electrical power to operate and is capable of producing power gain.
The term “amorphous material” is herein understood to mean a material that does not comprise a periodic lattice of atomic elements, or lacks mid-range (over distances of 10's of nanometers) to long-range crystalline order (over distances of 100's of nanometers).
The term “bucket” is herein understood to refer to a bank of transistors on an integrated circuit (“IC”) that tuned to provide the desired functional performance at a specific subset of signal parameters (voltage, frequency, etc.) that fall within the overall range of signal tolerances the IC is designed to operate within.
The terms “chemical complexity”, “compositional complexity”, “chemically complex”, or “compositionally complex” are herein understood to refer to a material, such as a metal or superalloy, compound semiconductor, or ceramic that consists of three (3) or more elements from the periodic table.
The term “chip carrier” is herein understood to refer to an interconnect structure built into a semiconductor substrate that contains wiring elements and active components that route electrical signals between one or more integrated circuits mounted on chip carrier's surface and a larger electrical system that they may be connected to.
The term “DDMOSFET” herein references its conventional meaning as a double-diffused dopant profile in conjunction with a field-effect transistor that uses a metal-oxide-semiconductor interface to modulate currents.
The terms “discrete assembly” or “discretely assembled” is herein understood to mean the serial construction of an embodiment through the assembly of a plurality of pre-fabricated components that individually comprise a discrete element of the final assembly.
The term “electroceramic” is herein understood to mean its conventional definition as being a complex ceramic material that has robust dielectric properties that augment the field densities of applied electrical or magnetic stimulus.
The term “emf” is herein understood to mean its conventional definition as being an electromotive force.
The term “EMI” is herein understood to mean its conventional definition as electromagnetic interference.
The term “FET” is herein understood to refer to its generally accepted definition of a field effect transistor wherein a voltage applied to an insulated gate electrode induces an electrical field through insulator that is used to modulate a current between a source electrode and a drain electrode.
The term “IGBT” herein references its conventional meaning as an insulated gate bipolar transistor.
The teen “integrated circuit” is herein understood to mean a semiconductor chip into which a large, very large, or ultra-large number of transistor elements have been embedded.
The term “LCD” for Liquid Chemical Deposition is herein understood to mean a method that uses liquid precursor solutions to fabricate materials of arbitrary compositional or chemical complexity as an amorphous laminate or free-standing body or as a crystalline laminate or free-standing body that has atomic-scale chemical uniformity and a microstructure that is controllable down to nanoscale dimensions.
The term “liquid precursor solution” is herein understood to mean a solution of hydrocarbon molecules that also contains soluble metalorganic compounds that may or may not be organic acid salts of the hydrocarbon molecules into which they are dissolved.
The term “microstructure” is herein understood to define the elemental composition and physical size of crystalline grains forming a material substance.
The term “MISFET” is herein understood to mean its conventional definition by referencing a metal-insulator-semiconductor field effect transistor.
The term “mismatched materials” is herein understood to define two materials that have dissimilar crystalline lattice structure, or lattice constants that differ by 5% or more, and/or thermal coefficients of expansion that differ by 10% or more.
The term “MOSFET” is herein understood to mean its conventional definition by referencing a metal-oxide-silicon field effect transistor.
The term “nanoscale” is herein understood to define physical dimensions measured in lengths ranging from 1 nanometer (nm) to 100's of nanometers (nm).
The term “power FET” is herein understood to refer to the generally accepted definition for a large signal vertically configured MOSFET and covers multi-channel (MUCHFET), V-groove MOSFET, truncated V-groove MOSFET, double-diffusion DMOSFET, superjunction, heterojunction FET or HETFET, and insulated-gate bipolar transistors (IGBT).
The term “surface FET”, also known as “lateral FET”, is herein understood to understood by its conventional definition as a field effect transistor that uses electrodes applied to, and electronic dopant profiles patterned on the surface of and within a semiconductor layer to modulate current flows across the surface of the semiconductor layer.
The term “standard operating temperatures” is herein understood to mean the range of temperatures between −40° C. and +125° C.
The terms “tight tolerance” or “critical tolerance” are herein understood to mean a performance value, such as a capacitance, inductance, or resistance that varies less than ±1% from the rated design value over standard operating temperatures.
In view of the above discussion, it would be beneficial to improve the performance of a power FET, or any FET, by allowing it modulate arbitrarily high current levels at arbitrarily high switching speeds, or to achieve efficient operation at any switching frequency or band of frequencies. The present invention instructs methods to fabricate a resonant transistor gate and its monolithic integration into a low-loss high-power, high-speed switched-mode power management module or a semiconductor carrier to improve the operational efficiency of co-located semiconductor die, including graphical processor units (GPU) or central processor units (CPU) or memory units, in electrical communication with the power management module or fully integrated semiconductor carrier.